1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory comprising a memory cell array including memory cells holding data.
2. Description of the Background Art
In general, volatile and nonvolatile memories are known as semiconductor memories. A DRAM (dynamic random access memory) is known as the volatile memory, while a flash EEPROM (electrically erasable and programmable read only memory) is known as the nonvolatile memory. The DRAM and the flash EEPROM allowing high integration are widely used.
FIG. 38 is an equivalent circuit diagram showing the structure of each memory cell 103 of a conventional DRAM. FIG. 39 is a sectional view showing a trench-type capacitor employed in the conventional DRAM. Referring to FIG. 38, the memory cell 103 of the DRAM employed as the conventional volatile memory is constituted of a selection transistor 101 and a capacitor 102. The capacitor 102 stores information of the memory cell 103 in the form of charges. In order to read the information from the memory cell 103, a word line WL rises to turn on the selection transistor 101, thereby capacitively coupling a cell capacitance Ccell and a bit line capacitance Cbl with each other. Thus, a bit line potential decided by the quantity of charges stored in the memory cell 103 can be read.
In order to ensure the cell capacitance Ccell of the capacitor 102 in the memory cell 103 of the conventional DRAM having the aforementioned structure also when the DRAM is refined, the trench type capacitor formed by vertically elongating an upper electrode 102a, a lower electrode 102c and a dielectric film 102b constituting the capacitor 102 is employed as shown in FIG. 39. When the conventional DRAM is further refined, however, it is difficult to ensure the cell capacitance Ccell of the capacitor 102 by employing the trench type capacitor shown in FIG. 39. In other words, integration of the DRAM through reduction of the design rule is approaching the limit.
In the flash EEPROM (hereinafter referred to as a flash memory) employed as the nonvolatile memory, a stacked or split gate memory cell of a CHE (channel hot electron) write system is limited in refinement of the channel length. In a memory cell of an FN (Fowler-Nordheim) write system such as a NAND type memory cell, the limit of refinement is equivalent to that of a logic transistor. However, the flash memory requires a high voltage of 15 V to 20 V for operation, and reduction of a power supply voltage for the logic transistor leads to reduction of efficiency for forming the high voltage of 15 V to 20 V from the low power supply voltage. Therefore, power consumption as well as the area of a charge pumping part are increased to disadvantageously inhibit the refinement.
On the other hand, a ferroelectric memory is known as one of recently noted nonvolatile memories, as disclosed in Japanese Patent Laying-Open No. 2001-210795, for example. This ferroelectric memory utilizes pseudo capacitance change responsive to the direction of polarization of a ferroelectric substance as a memory element. This ferroelectric memory, capable of rewriting data at a high speed with a low voltage in principle, is spotlighted as an ideal memory having both of the advantages of the DRAM and the flash memory, i.e., high-speed low-voltage operability and nonvolatility.
Memory cell systems for a ferroelectric memory are roughly classified into three types, i.e., a one-transistor one-capacitor system, a simple matrix system and a one-transistor system. FIG. 40 is an equivalent circuit diagram showing a memory cell 113 of a one-transistor one-capacitor ferroelectric memory. FIG. 41 is an equivalent circuit diagram showing a memory cell array of a simple matrix ferroelectric memory. FIG. 42 is a hysteresis diagram for illustrating operations of the simple matrix ferroelectric memory, and FIG. 43 is a hysteresis diagram for illustrating disturbance in the simple matrix ferroelectric memory. FIG. 44 is an equivalent circuit diagram showing memory cells 131 of a one-transistor ferroelectric memory.
As shown in FIG. 40, the memory cell 113 of the one-transistor one-capacitor ferroelectric memory is constituted of a selection transistor 111 and a dielectric capacitor 112, similarly to the memory cell 103 of the DRAM. The memory cell 113 is different from the memory cell 103 in a point that the same has the ferroelectric capacitor 112. In operation, a word line WL rises to turn on the selection transistor 111, thereby connecting a capacitance Ccell of the ferroelectric capacitor 112 and a bit line capacitance Cbl with each other. Then, a plate line PL is pulse-driven to feed charges to a bit line BL in a quantity varying with the direction of polarization of the ferroelectric capacitor 112. Data is read as the potential difference of the bit line BL, similar to the case of the DRAM.
In this one-transistor one-capacitor ferroelectric memory, the ferroelectric capacitor 112 is limited in refinement due to the structure similar to the memory cell 103 of the DRAM. Therefore, the one-transistor one-capacitor ferroelectric memory is limited in integration similarly to the DRAM.
The simple matrix ferroelectric memory is now described with reference to FIGS. 41 to 43. Each memory cell 121 of the simple matrix ferroelectric memory is constituted of a ferroelectric capacitor 122 consisting of a corresponding word line WL and a corresponding bit line BL extending to intersect with each other and a ferroelectric film (not shown) arranged between the word line WL and the bit line BL. First and second ends of the ferroelectric capacitor 122 are connected to the word line WL and the bit line BL respectively. This simple matrix ferroelectric memory, reading a potential resulting from capacitive coupling between the bit line BL and the ferroelectric capacitor 122, must ensure a capacitance similarly to the DRAM. However, the memory cell 121 is constituted of only the ferroelectric capacitor 122 with no selection transistor, whereby the simple matrix ferroelectric memory can be improved in degree of integration as compared with the one-transistor one-capacitor ferroelectric memory.
Operations of the simple matrix ferroelectric memory are now described with reference to FIGS. 42 and 43. Table 1 shows voltages applied to each memory cell 121 in reading and writing.
TABLE 1StandbyReadWrite “1”Write “0”Selected WL½ VccVcc0VccNonselected WL½ Vcc⅓ Vcc⅔ Vcc⅓ VccSelected BL½ Vcc0 → FIoatingVcc0Nonselected½ Vcc⅔ Vcc⅓ Vcc⅔ VccBL
In a write operation, both ends of each ferroelectric capacitor 122 are at the same potential in a standby state. In order to write data “0” in any memory cell 121, the ferroelectric memory applies Vcc and 0 V to the corresponding word line WL and the corresponding bit line BL respectively. At this time, the ferroelectric memory applies a potential difference Vcc to the ferroelectric capacitor 122. Thus, the ferroelectric memory makes a transition to a point A in FIG. 42. Thereafter the ferroelectric memory sets both ends of the ferroelectric capacitor 122 to the same potential, thereby making a transition to a point “0” in FIG. 42. In order to write data “1”, on the other hand, the ferroelectric memory applies 0 V and Vcc to the word line WL and the bit line BL respectively. At this time, the ferroelectric memory applies a potential difference −Vcc to the ferroelectric capacitor 122. Thus, the ferroelectric memory makes a transition to a point B in FIG. 42. Thereafter the ferroelectric memory sets both ends of the ferroelectric capacitor 122 to the same potential, thereby making a transition to a point “1” in FIG. 42.
In a read operation, the ferroelectric memory precharges the corresponding bit line BL to 0 V and thereafter brings the same into a floating state. Then, the ferroelectric memory activates the corresponding word line WL to Vcc. Assuming that CFE and CBL represent the capacitance of the ferroelectric capacitor 122 and the parasitic capacitance of the bit line BL respectively, this potential difference Vcc is capacitively divided by CFE and CBL. The capacitance CFE of the ferroelectric capacitor 122 can be approximated as C0 or C1 depending on the held data. Therefore, the potential of the bit line BL is expressed in the following formula (1) or (2):V0={C0/(C0+CBL)}×Vcc  (1)V1={C1/(C1+CBL)}×Vcc  (2)
The above formula (1) expresses the potential V0 of the bit line BL corresponding to the memory cell 121 holding the data “0”, while the above formula (2) expresses the potential V1 of the bit line BL corresponding to the memory cell 121 holding the data “1”.
A read amplifier determines the potential difference between the bit line potentials V0 and V1 expressed in the above formulas (1) and (2), thereby reading the data. In this data reading, the data in the memory cell 121 is destroyed. Therefore, the ferroelectric memory performs a write (restore) operation responsive to the read data after the data reading.
In the simple matrix ferroelectric memory, however, data of nonselected memory cells 121 disadvantageously disappear through disturbance. The simple matrix ferroelectric memory applies a potential difference ⅓ Vcc to all nonselected memory cells 121 in writing and reading. As shown in FIG. 43, therefore, the quantity of polarization is reduced due to the hysteretic property of the ferroelectric substance, leading to disappearance of data.
The one-transistor ferroelectric memory is now described with reference to FIGS. 40, 42 and 44. As shown in FIG. 44, each memory cell 131 of the one-transistor ferroelectric memory is formed by connecting a ferroelectric capacitor 132 to the gate of a MOS transistor 133. In this one-transistor ferroelectric memory, the ferroelectric capacitor 132 has first and second ends connected to a corresponding word line WL and the gate of the MOS transistor 133 constituting a cell transistor respectively. In this one-transistor ferroelectric memory, the threshold potential difference of the MOS transistor 133 varies with the direction of polarization of the ferroelectric capacitor 132, to vary a memory cell current. The one-transistor ferroelectric memory determines this variation of the memory cell current, thereby reading data. In the one-transistor ferroelectric memory reading data by detecting the memory cell current, the capacitance of the ferroelectric capacitor 132 may not be increased to some extent in consideration of a bit line capacitance, dissimilarly to the one-transistor one-capacitor ferroelectric memory shown in FIG. 40. Thus, the ferroelectric capacitor 132 can be so reduced in size that the one-transistor ferroelectric memory is suitable for refinement.
Operations of the one-transistor ferroelectric memory are now described. The one-transistor ferroelectric memory exhibits a hysteresis curve similar to that of the aforementioned simple matrix ferroelectric memory, and hence the operations thereof are described with reference to FIG. 42. In a standby state, all word lines WL, all bit line BL and all source lines SL are at 0 V. In order to write data “0” in any memory cell 131 in a write operation, the ferroelectric memory applies a step-up potential difference Vpp to the corresponding word line WL. At this time, the ferroelectric memory applies the potential Vcc capacitively divided with the gate capacitance of the MOS transistor 133 to the ferroelectric capacitor 132. Thus, the ferroelectric memory makes a transition to a point A shown in FIG. 42 despite the initial state. Thereafter the ferroelectric memory returns the word line WL to 0 V, and makes a transition to the data “0” shown in FIG. 42. In order to write data “1” in any memory cell 131, on the other hand, the ferroelectric memory applies 0 V and Vpp to the corresponding word line WL and the corresponding bit line BL respectively. In this case, the ferroelectric memory applies a potential difference −Vcc to the ferroelectric capacitor 132, thereby making a transition to a point B shown in FIG. 42. Thereafter the ferroelectric memory returns the bit line BL to 0 V, to make a transition to the data “1” shown in FIG. 42.
The one-transistor ferroelectric memory performs a read operation by activating the corresponding word line WL to a potential difference Vr causing no polarization inversion. Thus, the gate potential difference of the cell transistor (MOS transistor) 133 varies with the write state. A current flowing through the cell transistor 133 varies with the variation of the gate potential difference of the cell transistor 133, and hence the ferroelectric memory reads the current difference through the bit line BL. In other words, the one-transistor ferroelectric memory may read not the potential difference resulting from capacitive coupling between the capacitances of the ferroelectric capacitor 132 and the bit line BL but the current of the cell transistor 133, to require no polarization inversion in reading. Therefore, the one-transistor ferroelectric memory is capable of nondestructive reading. However, the one-transistor ferroelectric memory also exhibits the problem of disturbance of nonselected memory cells 131, similarly to the aforementioned simple matrix ferroelectric memory.
It is difficult to refine the conventional DRAM and the conventional flash memory as described above, and hence a memory cell system capable of higher integration is required. On the other hand, the highly integrable one-transistor and simple matrix ferroelectric memories have the aforementioned problem of disturbance resulting in disappearance of data from nonselected memory cells. Therefore, it is disadvantageously difficult to put the conventional one-transistor and simple matrix ferroelectric memories into practice.